Solid-state storage, such as NAND flash memory, stores data in arrays of storage cells, which, in the case of flash memory, are formed from floating-gate transistors. NAND flash memory devices return previously stored data by reading a set of bits from cells in an array. A memory device may include one or more chips, and a chip may include one or more arrays of memory cells (e.g., memory die).
The time required to erase data from a cell is typically longer than the time required to write data to a cell and typically much longer than the time required to read data from a cell. Write/program times are typically longer than read times, but shorter than erase times. One operation that is most critical to perceived performance is the program of data into flash. While erase times are typically much longer than program times, the write command is more often invoked than the erase command (e.g., since an entire erase block may be erased at a time, while single word lines may be programmed at a time).
One problem in program performance, is that many of the resources (e.g., hardware and/or firmware) that are allocated to single write operation may not be released for a relatively long time, as they may be allocated until the program operation is completely ended. As a result, a host may be unable to access the memory device until the program operation is confirmed and the resources released.
One challenge with current high-performance program operations is the peak power that is consumed during that program operation. When two or more die work in parallel, their peak power consumption accumulates and can cause a reduction of the voltage of the source power supply, resulting in power drop causing the memory device to be nonfunctioning and consequential loss of service to user.